Renesas SH7781 User Manual
Page 1666
Appendix
Rev.1.00 Jan. 10, 2008 Page 1636 of 1658
REJ09B0261-0100
Reset
Pin Name
(LSI level)
Pin Name
(Module level)
Related
Module I/O
Power
-on Manual Sleep
Module
Standby
Bus
Release
PCIRESET
PCIRESET PCIC
O
L O K
⎯
O
PERR*
3
PERR PCIC
I/O
PZ
K
K
⎯
K
Port Q1
GPIO
I/O
PZ
K
K
⎯
K
SERR PCIC
I/O
PZ
K
K
⎯
K
SERR*
3
Port Q0
GPIO
I/O
PZ
K
K
⎯
K
STOP PCIC
I/O
PZ
K
K
⎯
K
CDE DU
O
PZ
K
K
⎯
K
STOP/CDE*
3
Port P4
GPIO
I/O
PZ
K
K
⎯
K
TRDY PCIC
I/O
PZ
K
K
⎯
K
DISP DU
O
PZ
K
K
⎯
K
TRDY/DISP*
3
Port P2
GPIO
I/O
PZ
K
K
⎯
K
CLKOUT CLKOUT CPG
O
O
K
K
⎯
K
CLKOUTENB CLKOUTENB CPG O H K
K
⎯
K
PRESET
PRESET RESET
I
I
I I
⎯
I
NMI NMI INTC
I
PI
PI/I
PI/I
⎯
PI/I
MRESETOUT
(default)
RESET O H
L
O
⎯
O
MRESETOUT/
IRQOUT
IRQOUT INTC
O
H
O
O
⎯
O
IRQ/
IRL[3:0] IRQ/IRL[3:0] INTC I PI I
I
⎯
I
MODE0 (power-
on reset)
CPG I I
⎯
⎯
⎯
⎯
Port L4 (default) GPIO
I/O
⎯
K K
⎯
K
IRQ/
IRL4
INTC
I
⎯
I I
⎯
I
MODE0/
IRQ/
IRL4/
FD4
FD4 FLCTL
I/O
⎯
K K K K
MODE1 (power-
on reset)
CPG I I
⎯
⎯
⎯
⎯
Port L3 (default) GPIO
I/O
⎯
K K
⎯
K
MODE1
IRQ/
IRL5/
FD5
IRQ/
IRL5 INTC
I
⎯
I I
⎯
I
FD5
FLCTL
I/O
⎯
K K K K