Renesas SH7781 - Manual (Page 290)

9. On-Chip Memory
Rev.1.00 Jan. 10, 2008 Page 260 of 1658
REJ09B0261-0100
9.4 On-Chip Memory Protective Functions
This LSI implements the following protective functions to the on-chip memory by using the on-
chip memory access mode bit (RMD) and the on-chip memory protection enable bit (RP) in the
on-chip memory control register (RAMCR).
• Protective functions for access from the CPU and FPU
When RAMCR.RMD = 0, and the on-chip memory is accessed in user mode, it is determined
to be an address error exception.
When MMUCR.AT = 1 and RAMCR.RP = 1, MMU exception and address error exception are
checked in the on-chip memory area which is a part of area P4 as with the area P0/P3/U0.
The above descriptions are summarized in table 9.6.
Table 9.6 Protective Function Exceptions to Access On-Chip Memory
MMUCR.AT RAMCR.RP SR.MD RAMCR. RMD
Always Occurring
Exceptions Possibly Occurring
Exceptions
0 Address error
exception
— 0
1 — —
0 x
1 x — —
0 Address error
exception
— 0
1 — —
0
1 x — —
0 Address error
exception
—
1
1 0
1 — MMU exception
1 x — MMU exception
Legend: x: Don't care