Renesas SH7781 User Manual
Page 633
13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 603 of 1658
REJ09B0261-0100
(7)
PCI Interrupt Mask Register (PCIIMR)
This register is the mask register for PCIIR.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
Bit:
Initial value:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MRD
PEIM
MW
PDIM
MAD
IMM
TAD
IMM
PEDI
TRM
DPEI
TWM
SDIM
APE
DIM
MDE
IM
TMT
OIM
—
—
—
—
—
TTA
DIM
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
Bit:
Initial value:
Bit Bit
Name
Initial
Value R/W
Description
31 to 15
⎯
All 0
SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
14 TTADIM
0 SH:
R/W
PCI: R
Target Target-Abort Interrupt Mask
0: TTADI disabled (masked)
1: TTADI enabled (not masked)
13 to 10
⎯
All 0
SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
9 TMTOIM
0
SH:
R/W
PCI: R
Target Retry Time Out Interrupt Mask
0: TMTOI disabled (masked)
1: TMTOI enabled (not masked)
8 MDEIM
0
SH:
R/W
PCI: R
Master Function Disable Error Interrupt Mask
0: MDEI disabled (masked)
1: MDEI enabled (not masked)
7 APEDIM
0
SH:
R/W
PCI: R
Address Parity Error Detection Interrupt Mask
0: APEDI disabled (masked)
1: APEDI enabled (not masked)