Renesas SH7781 - Manual (Page 165)

6. Floating-Point Unit (FPU)
Rev.1.00 Jan. 10, 2008 Page 135 of 1658
REJ09B0261-0100
DR (2i)
FR (2i) FR (2i+1)
8n+4 8n+7 8n 8n+3
63 0
63 32 31 0
Floating-point register
Memory area
63 0
Floating-point register
Memory area
DR (2i)
FR (2i) FR (2i+1)
4n 4m 4n+3 4m+3
63 0
63 32 31 0
DR (2i)
FR (2i+1) FR (2i)
8n+4 8n+7 8n+3 8n
63 0
63 32 31 0
(1) SZ = 0 (2) SZ = 1, PR = 0
63 0 63 0
DR (2i)
FR (2i+1) FR (2i)
8n 8n+3 8n+7 8n+4
63 0
63 32 31 0
(3) SZ = 1, PR = 1
63 0
* 1 , * 2 * 2
Notes: 1. In the case of SZ = 0 and PR = 0, DR register can not be used.
2. The bit-location of DR register is used for double precision format when PR = 1.
(In the case of (2), it is used when PR is changed from 0 to 1.)
Figure 6.5 Relation between SZ Bit and Endian