Renesas SH7781 - Manual (Page 336)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 306 of 1658
REJ09B0261-0100
Module
Relation between Setting/Clearing Interrupt Source of
Module and Indication by INT2A0 and INT2A1
DMAC Interrupt sources
DMAE0, DMAE1
When the DMAE0 or DMAE1 interrupt source bit (i.e. the AE bit
in DMAOR0 or DMAOR1) is set, the same interrupt status
information is read from registers DMAOR0 and DMAOR1 and
registers INT2A0 and INT2A1. This means that the time
required for reflection in INT2A0 and INT2A1 is guaranteed by
hardware.
When the DMAE0 or DMAE1 interrupt source is cleared, the
time required for reflection in INT2A0 and INT2A1 is
guaranteed by dummy reading DMAOR0 or DMAOR1 once
after writing to DMAOR0 or DMAOR1.
Interrupt sources
DMINT0 to
DMINT11
Setting of the HE and TE bits in CHCR0 to CHCR11 and output
of interrupt request to the INTC take place with different timing.
For details, see section 14, Direct Memory Access Controller
(DMAC).
When interrupt sources, DMINT0 to DMINT11 (corresponding
to bits HE and TE in CHCR0 to CHCR11) are cleared, the time
required for reflection in INT2A0 and INT2A1 is guaranteed by
dummy-reading CHCR0 to CHCR11 once after writing to
CHCR0 to CHCR11 that indicate generation of interrupt
requests.
Note: The registers in the modules that indicate generation of interrupt requests are as follows.
WDT: WDTCSR
TMU: TCR0 to TCR5
SCIF: SCFSR0 to SCFSR6, SCLSR0 to SCLSR6
HSPI: SPSR
SIOF: SISTR
MMCIF: INTSTR0 to INTSTR2
DU: DSSR
SSI: SSISR
HAC: HACTSR, HACRSR
FLCTL: FLINTDMACR, FLTRCR