Renesas SH7781 - Manual (Page 637)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 607 of 1658
REJ09B0261-0100
(10) PCI Arbiter Interrupt Register (PCIAINT)
In host mode, this register records interrupt sources. When multiple interrupts occur, only the first
source is registered. When an interrupt is disabled, the source is written to the corresponding bit in
this register, and, no interrupt occurs.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit:
Initial value:
R R R R R R R R R R R R R R R R
R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — — — — — — — — — — — — — —
R/WC R/WC R/WC R/WC R R R R R R R R/WC R/WC R/WC R R
R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WD
PEI RD
PEI
MAI TAI — — — — — — —
MB
TOI
TB
TOI
MBI — —
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit:
Initial value:
Bit Bit Name
Initial
Value R/W
Description
31 to 14
⎯
All 0 SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
13 MBI 0 SH: R/WC
PCI: R
Master-Broken Interrupt
An interrupt is detected when the master that received
the bus mastership did not start transaction
(
PCIFRAME is not asserted) within 16 clock cycles.
0: A master-broken interrupt was not generated
1: A master-broken interrupt was generated
12 TBTOI 0 SH: R/WC
PCI: R
Target Bus Time-Out Interrupt
An interrupt is detected when
TRDY or STOP is not
asserted within 16 clock cycles in the first data
transfer or 8 clock cycles in the second and
subsequent data transfer.
0: A target bus timeout interrupt was not generated
1: A target bus timeout interrupt was generated