Renesas SH7781 - Manual (Page 1185)

23. Serial Peripheral Interface (HSPI)
Rev.1.00 Jan. 10, 2008 Page 1155 of 1658
REJ09B0261-0100
23.3.1 Control Register (SPCR)
SPCR is a 32-bit readable/writable register that controls the transfer data of shift timing and
specifies the clock polarity and frequency.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
— — — — — — — — — — — — — — — —
R R R R R R R R R R R R R R R R
Bit:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0
CLKC0 CLKC1 CLKC2 CLKC3 CLKC4 IDIV CLKP FBS — — — — — — — —
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W
Description
31 to 8
⎯ All
0 R Reserved
These bits are always read as an undefined value. The
write value should always be 0.
7 FBS 0 R/W First Bit Start
Controls the timing relationship between each bit of
transferred data and the serial clock.
0: The first bit transmitted from the HSPI module is set
up such that it can be sampled by the receiving device at
the first edge of HSPI_CLK specified by the register after
the HSPI_CS pin goes low. Similarly the first received bit
is sampled at the first edge of HSPI_CLK after the
HSPI_CS pin goes low.
1: The first bit transmitted from the HSPI module is set
up such that it can be sampled by the receiving device at
the second edge of HSPI_CLK after the HSPI_CS pin
goes low. Similarly the first received bit is sampled at the
second edge of HSPI_CLK specified by the register after
the HSPI_CS pin goes low.
6 CLKP 0 R/W Serial Clock Polarity
0: HSPI_CLK signal is not inverted and so is low when
inactive.
1: HSPI_CLK signal is inverted and so is high when
inactive.