Renesas SH7781 - Manual (Page 763)

15. Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 733 of 1658
REJ09B0261-0100
Section 15 Clock Pulse Generator (CPG)
The CPG generates clocks provided to the internal and external bus interfaces of the SH7785, and
controls power-down mode. The CPG consists of a crystal oscillator circuit, PLLs, dividers, and
the control unit.
15.1 Features
The CPG has the following features.
• Generates SH7785 internal clocks*
Generates the CPU clock (Ick) used in the CPU, FPU, cache, and TLB; the SuperHyway clock
(SHck) used in the SuperHyway, the
GDTA clock (GAck) used in the graphic data translation
accelerator, the DU clock (DUck) used in the display unit; the peripheral clock (Pck) used in
the interface with on-chip peripheral modules; and the RAM clock (Uck) used in URAM
• Generates SH7785 external clocks
Generates the bus clock (Bck) used in the interface with the external devices, and the DDR
clock (DDRck) for the memory clock used in the DBSC2.
• Clock operating modes
Selects a crystal resonator or an external clock input for the clock input to the CPG
• Controls power-down mode
Can stop the CPU in sleep mode and specific modules in module standby mode. For details,
see section 17, Power-Down Mode.
Figure 15.1 shows a block diagram of the CPG.
Note: * For description of the clock used by each module, see the sections on individual
modules.