Renesas SH7781 - Manual (Page 474)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 444 of 1658
REJ09B0261-0100
TAS1
CLKOUT
A25-A0
CSn
R/ W
WEn
(In reading)
(In writing)
D63-D0
T1 TS1 Tw Tw Tw T2 Tw TH1 TH2 TAH1
* 1
* 2
TS1: CSn assertion - RD assertion delay cycle
CSnWCR RDS = 001
TAS1: Address setup wait
CSnWCR ADS=001
TAH1: Address hold wait
CSnWCR AHS = 001
Tw: Access wait
CSnWCR IW = 0100
TH1, TH2: RD negation - CSn negation delay cycle
CSnWCR RDH = 010
WEn
D63 to D0
(ADS=000)
BS
TS1: CSn assertion - WEn assertion delay cycle
CSnWCR WTS = 001
TAS1: Address setup wait
CSnWCR BSH=001
TAH1: Address hold wait
CSnWCR ADH = 001
Tw: Access wait
CSnWCR IW = 0100
TH1, TH2: WE negation - CSn negation delay cycle
CSnWCR WTH = 010
CLKOUT CLKOUT
D63 to D0
(ADS=001 to 111)
Notes: 1. When CSnBCR RDSPL is set to 1
2. When CSnWCR BSH is set to 1
Figure 11.39 Wait State Timing of Byte Control SRAM