Renesas SH7781 - Manual (Page 904)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 874 of 1658
REJ09B0261-0100
19.3.19 CLAMP Signal Start Register (CLAMPSR)
The CLAMP signal start register (CLAMPSR) sets the rising edge position of the CLAMP signal.
For timing charts for the CLAMP signal and the DE signal, refer to section 19.5.6, CLAMP Signal
and DE Signal.
The value is retained during power-on reset and manual reset.
R/W:
Internal update:
R/W:
Internal update:
Bit:
Initial value:
Bit:
Initial value:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — — — — — — — — — — — — — —
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R
O O O O O O O O O O O
— — — — — — — — — — — 0 0 0 0 0
CLAMPS — — — — —
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
Bit Bit Name
Initial
Value R/W Internal
Update Description
31 to 11
⎯ All
0 R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 0 CLAMPS Undefined R/W Yes Clamp Signal Start
The CLAMP signal rising edge position should
be set in dot clock units relative to the falling
edge of the HSYNC signal.
The CLAMP signal rises (setting + 1) cycles
after the falling edge of the HSYNC signal.
Hence the CLAMP signal cannot be made to
rise in the same cycle as the falling edge of the
HSYNC signal.