Renesas SH7781 - Manual (Page 774)

15. Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 744 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
11
10
9
8
S2FC3
S2FC2
S2FC1
S2FC0
0
0
0
0
R/W
R/W
R/W
R/W
Frequency division ratio of the GDTA clock (GAck)
0000: No change
0100:
Ч 1/8
0101:
Ч 1/12
Others: Setting prohibited
7
6
5
4
S3FC3
S3FC2
S3FC1
S3FC0
0
0
0
0
R/W
R/W
R/W
R/W
Frequency division ratio of the DU clock (DUck)
0000: No change
0100:
Ч 1/8
0101:
Ч 1/12
0110:
Ч 1/16
0111:
Ч 1/18
1000:
Ч 1/24
1001:
Ч 1/32
1010:
Ч 1/36
1011:
Ч 1/48
Others: Setting prohibited
3
2
1
0
PFC3
PFC2
PFC1
PFC0
0
0
0
0
R/W
R/W
R/W
R/W
Frequency division ratio of the peripheral clock (Pck)
0000: No change
0111:
Ч 1/18
1000:
Ч 1/24
1001:
Ч 1/32
1010:
Ч 1/36
1011:
Ч 1/48
Others: Setting prohibited