Renesas SH7781 - Manual (Page 514)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 484 of 1658
REJ09B0261-0100
12.4.3 SDRAM Command Control Register (DBCMDCNT)
The SDRAM command control register (DBCMDCNT) is a readable/writable register. It is
initialized only upon power-on reset. The CMD2 to CMD0 bits in DBCMDCNT are always read
as 000.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R R R R R R R R R R R R R R R R
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CMD0 CMD1 CMD2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W R/W R/W R R R R R R R R R R R R R
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W
Description
31 to 3
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.