Renesas SH7781 - Manual (Page 766)

15. Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 736 of 1658
REJ09B0261-0100
15.2 Input/Output Pins
Table 15.1 shows the CPG pin configuration.
Table 15.1 CPG Pin Configuration
Pin Name Function I/O Description
MODE0,
MODE1,
MODE2,
MODE3,
and MODE4*
1
Mode Pins
0,1,2,3,4
Clock
operating
mode*
1
Input Select the clock operating mode
These pins are multiplexed with the following pins.
MODE0: the IRL4 (INTC), FD4 (FLCTL), and PL4 (GPIO) pins
MODE1: the IRL5 (INTC), FD5 (FLCTL), and PL3 (GPIO) pins
MODE2: the IRL6 (INTC), FD6 (FLCTL), and PL2 (GPIO) pins
MODE3: the IRL7 (INTC), FD7 (FLCTL), and PL1 (GPIO) pins
MODE4: the SCIF3_TXD (SCIF channel 3), FCLE (FLCTL), and PN5
(GPIO) pins
MODE10 Mode Pin 10
Clock input
mode*
1
Input Selects whether the crystal resonator is used
When MODE10 is set to the low level, the external clock is input from
the EXTAL pin.
When MODE10 is set to the high level, the crystal resonator is
connected directly to the EXTAL and XTAL pins.
MODE10 is multiplexed with the SCIF4_RXD (SCIF channel 4), FD2
(FLCTL), and PN1 (GPIO) pins.
XTAL Output Connected to a crystal resonator
EXTAL Input Used to input an external clock or connected to a crystal resonator.
CLKOUT* 2
Clock Pins
Output Used to output a local bus clock
CLKOUTENB Clock Output
Enabled
Output The low level is output when the output clock of the CLKOUT is
unstable.
When the input to the
PRESET pin is the low level, the high level is
output regardless of the status of the output clock on the CLKOUT
pin.
Notes: 1. The clock operating mode and the clock input mode depend on the states of the mode
pins on a power-on reset via the
PRESET pin.
2. For details on ensuring the AC timing of the CLKOUT pin, see the section about
electrical characteristics. Note the relationship between the input frequency and
multiplication rate of a crystal oscillator circuit.