Renesas SH7781 - Manual (Page 658)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 628 of 1658
REJ09B0261-0100
(27) PCI Cache Snoop Address Register 1 (PCICSAR1)
This register specifies the address to be compared with the PCI address requested by an external
PCI device to the PCIC. For details, see section 13.4.4 (7), Cache Coherency.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit:
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
CADR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
CADR
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit:
Initial value:
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Bit Name
Initial
Value R/W
Description
31 to 0 CADR H'0000
0000 SH: R/W
PCI: R/W
Address to be Compared
This register specifies the address to be compared
with the SuperHyway bus address that is requested
by an external device to the PCI