Renesas SH7781 - Manual (Page 215)

7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 185 of 1658
REJ09B0261-0100
(2) Software Processing (Instruction TLB Protection Violation Exception Handling
Routine)
Resolve the instruction TLB protection violation, execute the exception handling return instruction
(RTE), terminate the exception handling routine, and return control to the normal flow. The RTE
instruction should be issued at least one instruction after the LDTLB instruction.
7.6.4 Data TLB Multiple Hit Exception
A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual
address to which a data access has been made.
When a data TLB multiple hit exception occurs, a reset is executed, and cache coherency is not
guaranteed. The contents of PPN in the UTLB prior to the exception may also be corrupted.
(1)
Hardware Processing
In the event of a data TLB multiple hit exception, hardware carries out the following processing:
1. Sets the virtual address at which the exception occurred in TEA.
2. Sets exception code H'140 in EXPEVT.
3. Branches to the reset handling routine (H'A000 0000).
(2) Software Processing (Reset Routine)
The UTLB entries which caused the multiple hit exception are checked in the reset handling
routine. This exception is intended for use in program debugging, and should not normally be
generated.
7.6.5 Data TLB Miss Exception
A data TLB miss exception occurs when address translation information for the virtual address to
which a data access is made is not found in the UTLB entries. The data TLB miss exception
processing carried out by hardware and software is shown below.
(1) Hardware Processing
In the event of a data TLB miss exception, hardware carries out the following processing:
1. Sets the VPN of the virtual address at which the exception occurred in PTEH.
2. Sets the virtual address at which the exception occurred in TEA.