Renesas SH7781 - Manual (Page 1033)

20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 1003 of 1658
REJ09B0261-0100
20.3.22 MC Status Register (MCSR)
MCSR is in the MC register block and indicates the internal states of the MC.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MC_CFS MC_CFF
⎯ ⎯ ⎯ ⎯
MC_CFA
⎯ ⎯ ⎯ ⎯ ⎯
R R R R ⎯ ⎯ ⎯ ⎯ R R R ⎯ ⎯ ⎯ ⎯ ⎯
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 11
⎯ All
0
⎯ Reserved
These bits are always read as 0. The write value should
always be 0.
10 to 8 MC_CFA All 0 R Indicates the number of commands accumulated in
MCCF (command FIFO); maximum number accumulated
is 4
Number of accumulated commands:
000: 0
001: 1
010: 2
011: 3
100: 4
7 to 4
⎯ All
0
⎯ Reserved
These bits are always read as 0. The write value should
always be 0.
3 MC_CFF 0 R MCCF status display
Indicates the state of command buffer reception.
0: Command receivable
1: Command buffer full