Renesas SH7781 - Manual (Page 1369)

27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1339 of 1658
REJ09B0261-0100
Figure 27.1 shows a block diagram of the FLCTL.
DMAC
32
32
Flash interface
32
8
8
8
32 32
FLCTL
FCLK
QTSEL
FCKSEL
FLSTE (status error or ready busy
timeout error)
FLTEND (transfer end)
FLTRQ0 (FIFO0 transfer request)
FLTRQ1 (FIFO1 transfer request)
NAND-type
flash memory
FIFO
256 bytes
Ч1, Ч1/2,
Ч1/4
DMA transfer
requests
(2 lines)
Peripheral bus
Peripheral bus interface
Registers
Interrupt
control
Transmission/
reception
control
Control signal
Peripheral clock
Pck
•
•
•
•
Details of interrupt source
Figure 27.1 Block Diagram of FLCTL