Renesas SH7781 - Manual (Page 953)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 923 of 1658
REJ09B0261-0100
19.3.53 Output Signal Timing Adjustment Register (OTAR)
The output signal timing adjustment register (OTAR) selects the timing for the output signal.
For information on adjustment timing, refer to section 19.5.5, Output Signal Timing Adjustment.
R/W:
Internal update:
R/W:
Internal update:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit:
Initial value:
R R R R R/W R/W R/W R R/W R/W R/W R R/W R/W R R/W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — — DRGBA — CLAMPA — DEA —
R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SYNCA — DISPA — CDEA — — — — —
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit:
Initial value:
Bit Bit Name
Initial
Value R/W Internal
Update Description
31
⎯ 0 R ⎯ Reserved
This bit is always read as 0. The write value
should always be 0.