Renesas SH7781 - Manual (Page 622)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 592 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
2 IOCS 0 SH: R/W
PCI: R
INTA Output
Controls the
INTA output by software. This bit is valid
only when the PCIC operates in normal mode.
0: The
INTA pin is in the high-impedance state (driven
high by an on-chip pull-up resistor)
1: Asserts
INTA (output at low level)
1 RSTCTL 0 SH: R/W
PCI: R
PCIRST Output
Controls the
PCIRST pin state by setting this bit to 1.
The
PCIRST pin is output at low level at a power-on
reset.
0: Negates
PCIRST (output at high level)
1: Asserts
PCIRST (output at low level)
0 CFINIT 0 SH: R/W
PCI: R
PCIC Internal Register Initialization Control
This bit should be set to 1 after the PCIC internal
registers are initialized. Setting this bit enables
accesses from the PCI bus. During initialization in
host mode, the bus mastership is not given to the
other devices on the PCI bus. In normal mode, the
PCIC returns RETRY without accepting the access
from the PCI bus when it is accessed from the PCI
bus.
0: Initialization being performed
1: Initialization completed