Renesas SH7781 - Manual (Page 1148)

22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1118 of 1658
REJ09B0261-0100
22.3.8 Interrupt Enable Register (SIIER)
SIIER is a 16-bit readable/writable register that enables the issuance of SIOF interrupts. When
each bit in this register is set to 1 and the corresponding bit in SISTR is set to 1, the SIOF issues
an interrupt.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RF
OVFE
RF
UDFE
TF
UDFE
TF
OVFE
FS
ERRE
SA
ERRE
— —
RD
REQE
RF
FULE
RC
RDYE
RD
MAE
TDR
EQE TFE
MPE
TD
MAE
TCR
DYE
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
15 TDMAE 0 R/W Transmit Data DMA Transfer Request Enable
Transmits an interrupt as a CPU interrupt or a DMA
transfer request when the TDREQE bit is 1.
0: Used as a CPU interrupt
1: Used as a DMA transfer request to the DMAC
14 TCRDYE 0 R/W Transmit Control Data Ready Enable
0: Disables interrupts due to transmit control data ready
1: Enables interrupts due to transmit control data ready
13 TFEMPE 0 R/W Transmit FIFO Empty Enable
0: Disables interrupts due to transmit FIFO empty
1: Enables interrupts due to transmit FIFO empty
12 TDREQE 0 R/W Transmit Data Transfer Request Enable
0: Disables interrupts due to transmit data transfer
requests
1: Enables interrupts due to transmit data transfer
requests
11 RDMAE 0 R/W Receive Data DMA Transfer Request Enable
Transmits an interrupt as a CPU interrupt or a DMA
transfer request when the RDREQE bit is 1.
0: Used as a CPU interrupt
1: Used as a DMA transfer request to the DMAC