Renesas SH7781 - Manual (Page 400)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 370 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value
R/W Description
6 to 0 ASYNC[6:0] All 0 R/W Asynchronous Input
These bits enable asynchronous inputs of the
corresponding pins.
0: CLKOUT-synchronous inputs to the corresponding
pins
1: CLKOUT-asynchronous inputs to the corresponding
pins
ASYNC[6]:
DREQ3
ASYNC[5]:
DREQ2
ASYNC[4]:
DREQ1
ASYNC[3]:
DREQ0
ASYNC[2]:
IOIS16
ASYNC[1]:
BREQ
ASYNC[0]:
RDY
When asynchronous input is set (ASYNCn
= 1), the sampling timing is one cycle before the
synchronous input setting (see figure 11.4).
The timing shown in this section, other sections and section 32 Electrical Characteristics is that
with synchronous input setting (ASYNCn
= 0). Note that the setup/hold time must be satisfied
when synchronous input is set.
T1
CLKOUT
Tw Twe Tw T2
RDY
(BCR.ASYNC0 = 0)
RDY
(BCR.ASYNC0 = 1)
: Sampling Timing
Figure 11.4
RDY Sampling Timings with ASYNCn Settings
(Two Wait Cycles Inserted by CSnWCR.)