Renesas SH7781 - Manual (Page 538)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 508 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
18 DIC_DQ 0 R/W Data Pin Impedance value
This bit should be set to the same value as the value set
for DIC of EMRS(1) in the DDR2-SDRAM.
0: Normal
1: Weak
17 DIC_CK 0 R/W Clock Pin Impedance value
This bit should be set to the same value as the value set
for DIC of EMRS(1) in the DDR2-SDRAM.
0: Normal
1: Weak
16 DIC 0 R/W Impedance Value Set in the DIC of EMRS(1) in the
SDRAM
This bit should be set to the same value as the value set
for DIC of EMRS(1) in the DDR2-SDRAM.
0: Normal
1: Weak
15 to 13
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
If a value other than 0 is written, correct operation
cannot be guaranteed.
12, 11 ODTEN1
and
ODTEN0 00 R/W ODT Output Mode Switch
These bits switch the ODT output mode.
For details on the note when the ODTEN bits are set to
01, refer to section 12.5.9, Important Information
Regarding ODT Control Signal Output to SDRAM.
00: The ODT pin is fixed low regardless of WRITE
command issue.
01: The ODT pin is fixed high when the WRITE
command is issued.
10 and 11: The ODT pin is fixed high regardless of
WRITE command issue.