Renesas SH7781 - Manual (Page 323)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 293 of 1658
REJ09B0261-0100
(10) Interrupt Mask Clear Register 2 (INTMSKCLR2)
INTMSKCLR2 is a 32-bit write-only register that clears the mask settings for the IRL interrupt
requests for each input level pattern on the
IRL pins. Undefined values are read from this register.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
⎯ IC001 IC002 IC003 IC004 IC005 IC006 IC007 IC008 IC009 IC010 IC011 IC012 IC013 IC015 IC014
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
⎯ IC101 IC102 IC103 IC104 IC105 IC106 IC107 IC108 IC109 IC110 IC111 IC112 IC113 IC115 IC114
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
Bit Name
Initial
Value R/W Description
31 IC015 0 R/W Clears masking of the
interrupt source of
IRL3 to
IRL0 = LLLL (H'0).
30 IC014 0 R/W Clears masking of the
interrupt source of
IRL3 to
IRL0 = LLLH (H'1).
29 IC013 0 R/W Clears masking of the
interrupt source of
IRL3 to
IRL0 = LLHL (H'2).
28 IC012 0 R/W Clears masking of the
interrupt source of
IRL3 to
IRL0 = LLHH (H'3).
[When read]
Undefined values are
read.
[When written]
0: No effect
1: Clears the
corresponding interrupt
mask (enables the
interrupt)
27 IC011 0 R/W Clears masking of the
interrupt source of
IRL3 to
IRL0 = LHLL (H'4).
26 IC010 0 R/W Clears masking of the
interrupt source of
IRL3 to
IRL0 = LHLH (H'5).
25 IC009 0 R/W Clears masking of the
interrupt source of
IRL3 to
IRL0 = LHHL (H'6).
24 IC008 0 R/W Clears masking of the
interrupt source of
IRL3 to
IRL0 = LHHH (H'7).