Renesas SH7781 - Manual (Page 535)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 505 of 1658
REJ09B0261-0100
12.4.12 DDRPAD Frequency Setting Register (DBFREQ)
The DDRPAD frequency setting register (DBFREQ) is a readable/writable register. It is initialized
only upon power-on reset.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R R R R R R R R R R R R R R R R
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FREQ0 FREQ1 FREQ2
⎯ ⎯ ⎯ ⎯ ⎯
DLLRST
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W R/W R/W R R R R R R/W R R R R R R R
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W
Description
31 to 9
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
8 DLLRST 0 R/W DLL Reset Bit
Resets the DLL within DDRPAD. The FREQ bits should
be used to set the frequency when this bit is 0. If the
FREQ bit is changed when this bit is 1, correct
operation cannot be guaranteed.
0: Resets the frequency setting
1: Generates or retains the frequency setting
7 to 3
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.