Renesas SH7781 - Manual (Page 1633)

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1603 of 1658
REJ09B0261-0100
32.3.9 SCIF Module Signal Timing
Table 32.14 SCIF Module Signal Timing
Conditions: V
DDQ
= 3.0 to 3.6 V, V
DD
= 1.1 V, T
a
=
−40 to 85°C, C
L
= 30 pF, PLL2 on
Module Item Symbol Min. Max. Unit Figure
SCIFn Input clock cycle (asynchronous) t
Scyc
4 — t
Pcyc
Input clock cycle (clock synchronous) 10 — t
Pcyc
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 0.8 t
Pcyc
Input clock fall time t
SCKf
— 0.8 t
Pcyc
32.42
Transfer data delay time t
TXD
— 6 t
Pcyc
32.43
Receive data setup time
(clock synchronous) t
RXS
16 — ns
Receive data hold time
(clock synchronous) t
RXH
16 — ns
Note: t
pcyc
means one cycle time of the peripheral clock (Pck).
t
SCKW
t
Scyc t
SCKf
t
SCKr
SCIFn_CLK
Figure 32.42 SCIFn_CLK Input Clock Timing