Renesas SH7781 - Manual (Page 631)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 601 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
3 TADIM 0 SH: R/WC
PCI: R
Target Abort Detection Interrupt for Master
Indicates that transaction was terminated by a target
abort when the PCIC is a master.
0: A target abort interrupt was not generated when
the PCIC is a master
1: A target abort interrupt was generated when the
PCIC is a master
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
2 MADIM 0 SH: R/WC
PCI: R
Master-Abort Interrupt for Master
Indicates that transaction was terminated by a
master abort when the PCIC is a master
0: A master abort interrupt was not generated when
the PCIC is a master
1: A master abort interrupt was generated when the
PCIC is a master
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
1 MWPDI 0 SH: R/WC
PCI: R
Master Write
PERR Detection Interrupt
Indicates that the PCIC received
PERR from a target
during data write to the target and the PCIC is a
master.
Note: Master write
PERR is detected only when bit 6
(PER) in PCICMD is set to 1.
0: A master write
PERR detection interrupt was not
generated
1: A master write
PERR detection interrupt was
generated
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.