Renesas SH7781 - Manual (Page 344)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 314 of 1658
REJ09B0261-0100
10.3.4 Individual On-Chip Module Interrupt Source Registers (INT2B0 to INT2B7)
INT2B0 to INT2B7 are registers that indicate more details on each interrupt source, in addition to
the interrupt source that is corresponding to each module and is indicated in the interrupt source
register. INT2B0 to INT2B7 are 32-bit read-only registers that are not affected by the masked
state in the interrupt mask register. To mask each detailed source independently, set the interrupt
mask register of the corresponding module, or the interrupt enable register.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
— — — — — — — — — — — — — — — —
R R R R R R R R R R R R R R R R
Bit:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
— — — — — — — — — — — — — — — —
R R R R R R R R R R R R R R R R
Bit:
Initial value:
R/W:
(1) INT2B0: Detailed Interrupt Sources for the TMU
Module Bit Name Detailed Source Description
TMU 31 to 7
⎯ Reserved
These bits are read as 0
and cannot be modified.
6 TUNI5 TMU channel 5 underflow
interrupt
5 TUNI4 TMU channel 4 underflow
interrupt
4 TUNI3 TMU channel 3 underflow
interrupt
3 TICPI2 TMU channel 2 input
capture interrupt
2 TUNI2 TMU channel 2 underflow
interrupt
1 TUNI1 TMU channel 1 underflow
interrupt
TMU interrupt sources are
indicated. This register indicates
the TMU interrupt sources even if
the mask setting for TMU is made
in the interrupt mask register.
0 TUNI0 TMU channel 0 underflow
interrupt