Renesas SH7781 - Manual (Page 892)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 862 of 1658
REJ09B0261-0100
19.3.8 Display Unit Extensional Function Enable Register (DEFR)
The display unit extensional function enable register (DEFR) enables extension functions.
DEFR should be set during display reset (the DRES bit and DEN bit in DSYSR should be set to 1
and to 0 respectively) for external updates. If update is performed during display, the display may
flicker.
R/W:
Internal update:
R/W:
Internal update:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit:
Initial value:
R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — — — — — — — — — — — — — —
R/W R R R R/W R/W R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DSAE — — — ABRE DCKE — — — — — — — — — —
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit:
Initial value:
Bit Bit Name
Initial
Value R/W Internal
Update Description
31 to 6
⎯ All
0 R
⎯ Reserved
These bits are always read as undefined. The
write value should always be 0.
5 DCKE 0 R/W None Input Dot Clock Select Enable
0: The DCLKSEL bit and bit 4 of the FRQSEL
bits in the external sync control register
(ESCR) are disabled.
1: The DCLKSEL bit and bit 4 of the FRQSEL
bits in ESCR are enabled.
The following functions can be used.
• The clock from the DCLKIN pin and the DU
clock (DUck) can be selected as the input
dot clock. Selection is performed using the
DCLKSEL bit in ESCR.
• The dot clock frequency division ratio can be
selected in the range 0 to 32. The frequency
division ratio is set using the FRQSEL bits in
ESCR.