Renesas SH7781 - Manual (Page 715)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 685 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Descriptions
17 AM 0 R/W Acknowledge Mode
Selects whether DACK is output in a data read cycle or
in a data write cycle. DACK is output only for LBSC
space transfers.
This bit is valid in only CHCR0 to CHCR3.
0: DACK output in a read cycle
(DACK is output only when the DMA transfer source
is LBSC space.)
1: DACK output in a write cycle
(DACK is output only when the DMA transfer
destination is LBSC space.)
16 AL 0 R/W Acknowledge Level
Specifies whether the DACK signal output is high-active
or low-active. This bit is valid in only CHCR0 to CHCR3.
If DACK active direction has been changed, reflecting
the change on the external pins requires two cycles of
the external bus clock after writing to register is
completed.
0: DACK output low-active
1: DACK output high-active