Renesas SH7781 - Manual (Page 235)

7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 205 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
30 to 8
⎯ All
0 R Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
7 to 0 UB All 0 R/W Buffered Write Control for Each Area (64 Mbytes)
When writing is performed without using the cache or in
the cache write-through mode, these bits specify
whether the CPU waits for the end of writing for each
area.
0: The CPU does not wait for the end of writing
1: The CPU stalls and waits for the end of writing
UB[7]: Corresponding to the control register area
UB[6:0]: These bits are invalid in 32-bit address
extended mode.
(2) ITLB
The PPN field in the ITLB is extended to bits 31 to 10.
(3) UTLB
The PPN field in the UTLB is extended to bits 31 to 10. The same UB bit as that in the PMB is
added in each entry of the UTLB.
• UB: Buffered write bit
Specifies whether a buffered write is performed.
0: Buffered write (Subsequent processing proceeds without waiting for the write to complete.)
1: Unbuffered write (Subsequent processing is stalled until the write has completed.)
In a memory-mapped TLB access, the UB bit can be read from or written to by bit 9 in the data
array.
(4) PTEL
The same UB bit as that in the PMB is added in bit 9 in PTEL. This UB bit is written to the UB bit
in the UTLB by the LDTLB instruction. The PPN field is extended to bits 31 to 10.