Renesas SH7781 - Manual (Page 58)

2. Programming Model
Rev.1.00 Jan. 10, 2008 Page 28 of 1658
REJ09B0261-0100
Table 2.1 Initial Register Values
Type Registers Initial Value*
General registers R0_BANK0 to R7_BANK0,
R0_BANK1 to R7_BANK1,
R8 to R15
Undefined
SR MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0,
IMASK = B'1111, reserved bits = 0,
others = undefined
GBR, SSR, SPC, SGR, DBR Undefined
Control registers
VBR H'00000000
MACH, MACL, PR Undefined System registers
PC H'A0000000
Floating-point
registers FR0 to FR15, XF0 to XF15,
FPUL Undefined
FPSCR H'00040001
Note: * Initialized by a power-on reset and manual reset.
The CPU register configuration in each processing mode is shown in figure 2.2.
User mode and privileged mode are switched by the processing mode bit (MD) in the status
register.