Renesas SH7781 - Manual (Page 808)

16. Watchdog Timer and Reset (WDT)
Rev.1.00 Jan. 10, 2008 Page 778 of 1658
REJ09B0261-0100
(2) Power-On Reset Caused by Watchdog Timer Overflow in Sleep Mode
The timing of indicating the reset state or normal operation on the STATUS[1:0] pins is
synchronous with the peripheral clock (Pck), and is therefore asynchronous with the clocks input
from the EXTAL pin and the CLKOUT pin.
If the bus clock frequency has been changed from the initial value, the oscillation settling time of
PLL2 circuit and the time until the LSI resumes operation (WDT count up) are also required. In
this case, the WDT reset holding time is two peripheral clock (Pck) cycles or more.
WDT reset setup time WDT count up WDT reset
holding time
WDT overflow
signal
CLKOUT
output
STATUS[1:0]
output
HH (reset) LL (normal) HL (sleep)
PLL oscillation
settling time
EXTAL
input
CLKOUTENB
output
Figure 16.7 STATUS Output by Power-On Reset Caused by WDT Overflow
in Sleep Mode