Renesas SH7781 - Manual (Page 708)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 678 of 1658
REJ09B0261-0100
14.3.4 DMA Destination Address Registers B0 to B3, B6 to B9 (DARB0 to DARB3,
DARB6 to DARB9)
DARB are 32-bit readable/writable registers that specify the destination address of a DMA
transfer that is set in DAR again in repeat/reload mode. The data written to DAR by the CPU is
also written to DARB. To set the address that is different from DAR address, write data to DAR,
then, to DARB.
A word or longword boundary address should be specified when a word or longword transfer is
performed respectively. A 16-byte or 32-byte boundary value should be specified when a 16-byte
or 32-byte transfer is performed respectively.
The initial value of DARB is undefined.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt:
Initial value:
R/W: