Renesas SH7781 - Manual (Page 761)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 731 of 1658
REJ09B0261-0100
14.6.6 DACK/DREQ Setting
If the IWRRD, IWRRS, and IWW bits in CSnBCR are set to B'000 (no idle cycles), DACK of two
or more DMA transfers may be connected. If DACK of two or more DMA transfers is connected,
operation is not guaranteed under the following conditions. In these cases, set the IWRRD,
IWRRS, and IWW bits to B'001 to B'111 to insert a minimum of one idle cycle between DMA
transfers.
1. DMA transfer source is in the LBSC space, DMA transfer destination is not in the LBSC
space, DACK output (CHCR.AM
= 0) is set to a read cycle, and external request DREQ level
detection overrun 1 (cycle steal mode or burst mode) or external request DREQ edge detection
(cycle steal mode or burst mode) is set.
Prevent DACK of two or more DMA transfer units from connecting by setting the IWRRD
bits in CSnBCR to B'001 to B'111 (insert a minimum of one idle cycle in read-read cycles in
different space) and the IWRRS bits to B'001 to B'111 (insert a minimum of one idle cycle in
read-read cycles in the same space).
2. DMA transfer source is not in the LBSC space, DMA transfer destination is in the LBSC
space, DACK output (CHCR.AM
= 1) is set to a write cycle, and the external request DREQ
level detection overrun 1 (cycle steal mode or burst mode) or external request DREQ edge
detection (cycle steal mode or burst mode) is set.
Prevent DACK of two or more DMA transfer units from connecting by setting the IWW bits in
CSnBCR to B'001 to B'111 (insert a minimum of one idle cycle between write-read/write-
write cycles).