Renesas SH7781 - Manual (Page 1385)

27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1355 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
31 to 22 — All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
21, 20 FIFOTRG
[1:0] 00 R/W FIFO Trigger Setting
Change the condition for the FIFO transfer request.
(1) In reading flash memory
00: Issue an interrupt to the CPU or a DMA transfer
request when 4-byte data is written to
FLDTFIFO
01: Issue an interrupt to the CPU or a DMA transfer
request when 16-byte data is written to
FLDTFIFO
10: Issue an interrupt to the CPU or a DMA transfer
request when 128-byte data is written to
FLDTFIFO
11: Issue an interrupt to the CPU when FLDTFIFO
stores 128 bytes of data, or issue a DMA
transfer request when FLDTFIFO stores 16
bytes of data
(2) In writing flash memory
00: Issue an interrupt to the CPU when FLDTFIFO
has 4 bytes or more of empty area (do not set
DMA transfer)
01: Issue an interrupt or a DMA transfer request to
the CPU when FLDTFIFO has 16 bytes or more
of empty area
10: Issue an interrupt to the CPU when FLDTFIFO
has 128 bytes or more of empty area (do not
set DMA transfer)
11: Issue an interrupt to the CPU when FLDTFIFO
has 128 bytes or more of empty area, or issue a
DMA transfer request to the CPU when
FLDTFIFO has empty area of 16 bytes or more
19 AC1CLR 0 R/W FLECFIFO Clear
Clears the address counter of FLECFIFO.
0: Retains the address counter value of FLECFIFO. In
flash-memory access, clear this bit to 0.
1: Clears the address counter of FLECFIFO. After
clearing the counter, clear this bit to 0.