Renesas SH7781 - Manual (Page 539)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 509 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
10 ODT_
EARLY
0 R/W ODT Assertion Period Setting
Sets the ODT assertion period. The number of cycles is
the number of DDR clock cycles.
This setting is valid only when ODTEN is set to 01. In
order to extend ODT by 1 cycle using the setting of
ODT_EARLY, after setting CL to 5 or higher, the RDWR
bits in the DBTR2 register must be set to the value
specified in the data sheet for the DDR2-SDRAM, plus
1.
For details on the note when the ODTEN bits are set to
01, refer to section 12.5.9, Important Information
Regarding ODT Control Signal Output to SDRAM.
0: Asserts the ODT pin to high for 3 cycles for one write
command.
1: Asserts the ODT pin to high for 4 cycles for one write
command.
9, 8 T_ODT1
and
T_ODT0 00 R/W ODT Resistance Value Setting
These bits set the resistance value of the ODT
resistance within DDRPAD turned on for DDR2-SDRAM
reading. They should be set to the same value as the
Rtt set in EMRS(1) of DDR2-SDRAM.
00: ODT disabled
01: 75
Ω
10: 150
Ω
11: Setting prohibited (If specified, correct operation
cannot be guaranteed.)
7 to 3
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
If a value other than 0 is written, correct operation
cannot be guaranteed.
2 to 0
⎯ 111
R/W Reserved
These bits should always be written to 111. If these bits
are written to the value other than 111, correct operation
cannot be guaranteed.