Renesas SH7781 - Manual (Page 1170)

22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1140 of 1658
REJ09B0261-0100
(2) Reception in Master Mode
Figure 22.10 shows an example of settings and operation for master mode reception.
Start
End
Set the SCKE bit in SICTR to 1
Start SIOF_SCK output
Read SIRDR
Clear the RXE bit in SICTR to 0
RDREQ = 1
Transfer ended?
No
Yes
No
Yes
No.
1
2
3
4
5
6
7
8
Flowchart SIOF Settings SIOF Operation
Set operation start for baud rate generator
Output serial clock
Read receive data
Receive
Set to disable reception End reception
Set the start for frame synchronous signal
output and enable reception
Output frame
synchronous signal
Issue receive transfer
request according to
the receive FIFO
threshold value
Set SIMDR, SISCR, SITDAR,
SIRDAR, SICDAR, SITCR,
and SIFCTR
Set the FSE and RXE bits in SICTR to 1
Store SIOF_RXD receive data in SIRDR
synchronously with SIOF_SYNC
Set operating mode, serial clock, slot
positions for transmit/receive data, slot
position for control data, and FIFO
request threshold value
Figure 22.10 Example of Receive Operation in Master Mode