17 flctl module signal timing – Renesas SH7781 User Manual
Page 1648
32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1618 of 1658
REJ09B0261-0100
32.3.17
FLCTL Module Signal Timing
Table 32.22 NAND-Type Flash Memory Interface Timing
Item Symbol
Min.
Max.
Unit
Figure
Command issue setup time
t
NCDS
2 × t
fcyc
−10 —
ns
Command issue hold time
t
NCDH
1.5 × t
fcyc
−10 — ns
32.67, 32.71
Data output setup time
t
NDOS
0.5
t
fcyc
−10 —
ns
Data output hold time
t
NDOH
0.5
t
fcyc
−10 —
ns
32.67, 32.68,
32.70, 32.71
Command to address transition time 1 t
NCDAD1
1.5 × t
fcyc
−10 — ns
32.67,
32.68
Command to address transition time 2 t
NCDAD2
2 × t
fcyc
−10 —
ns 32.68
FWE cycle time
t
NWC
t
fcyc
−5 — ns
32.68,
32.70
FWE low pulse width
t
NWP
0.5
t
fcyc
−5 —
ns 32.67,
32.68,
32.70, 32.71
FWE high pulse width
t
NWH
0.5
t
fcyc
−5 —
ns 32.68,
32.70
Address to ready/busy transition time t
NADRB
—
32 × t
pcyc
ns 32.68,
32.69
Ready/busy to data read transition
time 1
t
NRBDR1
1.5 × t
fcyc
—
ns
Ready/busy to data read transition
time 2
t
NRBDR2
32 × t
pcyc
—
ns
FSC cycle time
t
NSCC
t
fcyc
—
ns
FSC high pulse width
t
NSPH
0.5 × t
fcyc
−5 —
ns
32.69
FSC low pulse width
t
NSP
0.5 × t
fcyc
−5 —
ns
Read data setup time
t
NRDS
24
—
ns
Read data hold time
t
NRDH
5
—
ns
32.69, 32.71
Data write setup time
t
NDWS
32 × t
pcyc
−10 —
ns
32.70
Command to status read transition
time
t
NCDSR
4 × t
fcyc
−10 —
ns 32.71
Command output off to status read
transition time
t
NCDFSR
3.5 × t
fcyc
—
ns
Status read setup time
t
NSTS
2.5 × t
fcyc
−10 ns
Notes: 1. t
pcyc
is the period of one peripheral clock (Pck) cycle.
2.
t
fcyc
is the period of one FLCTL clock (Fck) cycle.