Renesas SH7781 - Manual (Page 496)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 466 of 1658
REJ09B0261-0100
MCK0,
MCK1
MA[14:11]
MA[9:0]
MBA[2:0]
MCKE
MCS
MRAS
MCAS
MWE
MA[10]
Invalid
32-bit width: MDQS[3:0]
16-bit width: MDQS[1:0]
32-bit width: MDQ[31:0]
16-bit width: MDQ[15:0]
32-bit width: MDM[3:0]
16-bit width: MDM[1:0] Invalid
Invalid
Invalid
Invalid
READ
bank A
Invalid
Invalid
Invalid
SDRAM
command
Invalid
Invalid
Invalid
Invalid
Invalid Invalid
WRITE
bank A
Write data Read data
Valid
Valid
Valid
Valid
Valid
Valid
Example of CL = 3
High level
1 st 2 nd 3 rd 4 th 1 st 2 nd 3 rd 4 th
Figure 12.2 Burst Access Operation