Renesas SH7781 - Manual (Page 1107)

21. Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Jan. 10, 2008 Page 1077 of 1658
REJ09B0261-0100
Figure 21.8 shows a sample SCIF initialization flowchart.
Start of initialization
Clear TE and RE bits in
SCSCR to 0
Set TFCL and RFCL bits in
SCFCR to 1
Set CKE1 and CKE0 bits
in SCSCR (leaving TIE, RIE,
TE, and RE bits cleared to 0)
Set data transfer format
in SCSMR
Set value in SCBRR
1-bit interval elapsed?
Set RTRG1 and RTRG0,
TTRG1 and TTRG0, and
MCE bits in SCFCR, and
clear TFCL and RFCL bits to 0
Set TE and RE bits in
SCSCR to 1, and set TIE, RIE,
and REIE bits
End of initialization
Wait
No
Yes
Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE,
and RE to 0.
Set the data transfer format in
SCSMR.
Write a value corresponding to the
bit rate into SCBRR. (Not
necessary if an external clock is
used.)
Wait at least one bit interval, then
set the TE bit or RE bit in SCSCR
to 1. Also set the TIE, RIE, and
REIE bits.
Setting the TE and RE bits
enables the SCIF_TXD and
SCIF_RXD pins to be used.
When transmitting, the SCIF goes
to the mark state; when receiving,
it goes to the idle state, waiting for
a start bit.
[1]
[1]
[2]
[3]
[4]
[2]
[3]
[4]
Figure 21.8 Sample SCIF Initialization Flowchart