Renesas SH7781 - Manual (Page 345)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 315 of 1658
REJ09B0261-0100
(2) INT2B1: Detailed Interrupt Sources for the SCIF
Module Bit Name Detailed Source Description
SCIF 31 to 24
⎯ Reserved
These bits are read as 0
and cannot be modified.
23 TXI5 SCIF channel 5 transmit
FIFO data empty interrupt
22 BRI5 SCIF channel 5 break
interrupt or overrun error
interrupt
SCIF interrupt sources are
indicated. This register indicates
the SCIF interrupt sources even if
the mask setting for SCIF is made
in the interrupt mask register.
21 RXI5 SCIF channel 5 receive
FIFO data full interrupt or
receive data ready
interrupt
20 ERI5 SCIF channel 5 receive
error interrupt
19 TXI4 SCIF channel 4 transmit
FIFO data empty interrupt
18 BRI4 SCIF channel 4 break
interrupt or overrun error
interrupt
17 RXI4 SCIF channel 4 receive
FIFO data full interrupt or
receive data ready
interrupt
16 ERI4 SCIF channel 4 receive
error interrupt
15 TXI3 SCIF channel 3 transmit
FIFO data empty interrupt
14 BRI3 SCIF channel 3 break
interrupt or overrun error
interrupt
13 RXI3 SCIF channel 3 receive
FIFO data full interrupt or
receive data ready
interrupt
12 ERI3 SCIF channel 3 receive
error interrupt