Renesas SH7781 - Manual (Page 476)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 446 of 1658
REJ09B0261-0100
11.5.8 Wait Cycles between Access Cycles
When the external memory bus operating frequency is high, the turn-off of the data buffer
performed on completion of reading from a low-speed device may not be made in time. This cause
a collision with the next access data or a malfunction, which results in lower reliability. To prevent
this problem, the data collision prevention function is provided. With this function, the preceding
access area and the type of read/write are stored and a wait cycle is inserted before the access
cycle if there is a possibility that a bus collision occurs when the next access is started. As an
example of wait cycle insertion, idle cycles are inserted between the access cycles as shown in
section 11.4.3, CSn Bus Control Register (CSnBCR). By using bits IWW, IWRWD, IWRWS,
IWRRD and IWRRS in CSnBCR, at least the specified number of cycles can be inserted as idle
cycles.
When bus arbitration is performed, the bus is released after wait cycles are inserted between the
cycles.
When DMA transfer is performed in dual address mode, wait cycles are inserted as set in
CSnBCR idle cycle bits.
When consecutive accesses to the MPX interface area are performed after a read access, 1 wait
cycle is inserted even if the wait cycle is set to 0.
When the access size is 8-byte or 16-byte, wait cycles are inserted every 4-byte access.