Renesas SH7781 Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for SH7781 Renesas
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 1692 |
| Size: | 7.73 MB |
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Document Outline
- Cover
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- Preface
- Contents
- Section 1 Overview
- Section 2 Programming Model
- Section 3 Instruction Set
- Section 4 Pipelining
- Section 5 Exception Handling
- Section 6 Floating-Point Unit (FPU)
- Section 7 Memory Management Unit (MMU)
- 7.1 Overview of MMU
- 7.2 Register Descriptions
- 7.2.1 Page Table Entry High Register (PTEH)
- 7.2.2 Page Table Entry Low Register (PTEL)
- 7.2.3 Translation Table Base Register (TTB)
- 7.2.4 TLB Exception Address Register (TEA)
- 7.2.5 MMU Control Register (MMUCR)
- 7.2.6 Page Table Entry Assistance Register (PTEA)
- 7.2.7 Physical Address Space Control Register (PASCR)
- 7.2.8 Instruction Re-Fetch Inhibit Control Register (IRMCR)
- 7.3 TLB Functions (TLB Compatible Mode; MMUCR.ME = 0)
- 7.4 TLB Functions (TLB Extended Mode; MMUCR.ME = 1)
- 7.5 MMU Functions
- 7.6 MMU Exceptions
- 7.7 Memory-Mapped TLB Configuration
- 7.8 32-Bit Address Extended Mode
- 7.9 32-Bit Boot Function
- 7.10 Usage Notes
- Section 8 Caches
- Section 9 On-Chip Memory
- Section 10 Interrupt Controller (INTC)
- Section 11 Local Bus State Controller (LBSC)
- 11.1 Features
- 11.2 Input/Output Pins
- 11.3 Overview of Areas
- 11.4 Register Descriptions
- 11.5 Operation
- 11.5.1 Endian/Access Size and Data Alignment
- 11.5.2 Areas
- 11.5.3 SRAM interface
- 11.5.4 Burst ROM Interface
- 11.5.5 PCMCIA Interface
- 11.5.6 MPX Interface
- 11.5.7 Byte Control SRAM Interface
- 11.5.8 Wait Cycles between Access Cycles
- 11.5.9 Bus Arbitration
- 11.5.10 Master Mode
- 11.5.11 Slave Mode
- 11.5.12 Cooperation between Master and Slave
- 11.5.13 Power-Down Mode and Bus Arbitration
- 11.5.14 Mode Pin Settings and General Input Output Port Settings about Data Bus Width
- 11.5.15 Pins Multiplexed with Other Modules Functions
- 11.5.16 Register Settings for Divided-Up DACKn Output
- Section 12 DDR2-SDRAM Interface (DBSC2)
- 12.1 Features
- 12.2 Input/Output Pins
- 12.3 Data Alignment
- 12.4 Register Descriptions
- 12.4.1 DBSC2 Status Register (DBSTATE)
- 12.4.2 SDRAM Operation Enable Register (DBEN)
- 12.4.3 SDRAM Command Control Register (DBCMDCNT)
- 12.4.4 SDRAM Configuration Setting Register (DBCONF)
- 12.4.5 SDRAM Timing Register 0 (DBTR0)
- 12.4.6 SDRAM Timing Register 1 (DBTR1)
- 12.4.7 SDRAM Timing Register 2 (DBTR2)
- 12.4.8 SDRAM Refresh Control Register 0 (DBRFCNT0)
- 12.4.9 SDRAM Refresh Control Register 1 (DBRFCNT1)
- 12.4.10 SDRAM Refresh Control Register 2 (DBRFCNT2)
- 12.4.11 SDRAM Refresh Status Register (DBRFSTS)
- 12.4.12 DDRPAD Frequency Setting Register (DBFREQ)
- 12.4.13 DDRPAD DIC, ODT, OCD Setting Register (DBDICODTOCD)
- 12.4.14 SDRAM Mode Setting Register (DBMRCNT)
- 12.5 DBSC2 Operation
- 12.5.1 Supported SDRAM Commands
- 12.5.2 SDRAM Command Issue
- 12.5.3 Initialization Sequence
- 12.5.4 Self-Refresh Operation
- 12.5.5 Auto-Refresh Operation
- 12.5.6 Regarding Address Multiplexing
- 12.5.7 Regarding SDRAM Access and Timing Constraints
- 12.5.8 Important Information Regarding Use of 8-Bank DDR2-SDRAM Products
- 12.5.9 Important Information Regarding ODT Control Signal Output to SDRAM
- 12.5.10 DDR2-SDRAM Power Supply Backup Function
- 12.5.11 Method for Securing Time Required for Initialization, Self-Refresh Cancellation, etc.
- 12.5.12 Regarding the Supported Clock Ratio
- 12.5.13 Regarding MCKE Signal Operation
- Section 13 PCI Controller (PCIC)
- Section 14 Direct Memory Access Controller (DMAC)
- 14.1 Features
- 14.2 Input/Output Pins
- 14.3 Register Descriptions
- 14.3.1 DMA Source Address Registers 0 to 11 (SAR0 to SAR11)
- 14.3.2 DMA Source Address Registers B0 to B3, B6 to B9 (SARB0 to SARB3, SARB6 to SARB9)
- 14.3.3 DMA Destination Address Registers 0 to 11 (DAR0 to DAR11)
- 14.3.4 DMA Destination Address Registers B0 to B3, B6 to B9 (DARB0 to DARB3, DARB6 to DARB9)
- 14.3.5 DMA Transfer Count Registers 0 to 11 (TCR0 to TCR11)
- 14.3.6 DMA Transfer Count Registers B0 to B3, B6 to B9 (TCRB0 to TCRB3, TCRB6 to TCRB9)
- 14.3.7 DMA Channel Control Registers 0 to 11 (CHCR0 to CHCR11)
- 14.3.8 DMA Operation Register 0, 1 (DMAOR0 and DMAOR1)
- 14.3.9 DMA Extended Resource Selectors 0 to 5 (DMARS0 to DMARS5)
- 14.4 Operation
- 14.5 DMAC Interrupt Sources
- 14.6 Usage Notes
- Section 15 Clock Pulse Generator (CPG)
- Section 16 Watchdog Timer and Reset (WDT)
- Section 17 Power-Down Mode
- Section 18 Timer Unit (TMU)
- Section 19 Display Unit (DU)
- 19.1 Features
- 19.2 Input/Output Pins
- 19.3 Register Descriptions
- 19.3.1 Display Unit System Control Register
- 19.3.2 Display Mode Register (DSMR)
- 19.3.3 Display Status Register (DSSR)
- 19.3.4 Display Unit Status Register Clear Register (DSRCR)
- 19.3.5 Display Unit Interrupt Enable Register (DIER)
- 19.3.6 Color Palette Control Register (CPCR)
- 19.3.7 Display Plane Priority Register (DPPR)
- 19.3.8 Display Unit Extensional Function Enable Register (DEFR)
- 19.3.9 Horizontal Display Start Register (HDSR)
- 19.3.10 Horizontal Display End Register (HDER)
- 19.3.11 Vertical Display Start Register (VDSR)
- 19.3.12 Vertical Display End Register (VDER)
- 19.3.13 Horizontal Cycle Register (HCR)
- 19.3.14 Horizontal Sync Width Register (HSWR)
- 19.3.15 Vertical Cycle Register (VCR)
- 19.3.16 Vertical Sync Point Register (VSPR)
- 19.3.17 Equal Pulse Width Register (EQWR)
- 19.3.18 Separation Width Register (SPWR)
- 19.3.19 CLAMP Signal Start Register (CLAMPSR)
- 19.3.20 CLAMP Signal Width Register (CLAMPWR)
- 19.3.21 DE Signal Start Register (DESR)
- 19.3.22 DE Signal Width Register (DEWR)
- 19.3.23 Color Palette 1 Transparent Color Register (CP1TR)
- 19.3.24 Color Palette 2 Transparent Color Register (CP2TR)
- 19.3.25 Color Palette 3 Transparent Color Register (CP3TR)
- 19.3.26 Color Palette 4 Transparent Color Register (CP4TR)
- 19.3.27 Display Off Mode Output Register (DOOR)
- 19.3.28 Color Detection Register (CDER)
- 19.3.29 Background Plane Output Register (BPOR)
- 19.3.30 Raster Interrupt Offset Register (RINTOFSR)
- 19.3.31 Plane n Mode Register (PnMR) (n = 1 to 6)
- 19.3.32 Plane n Memory Width Register (PnMWR) (n = 1 to 6)
- 19.3.33 Plane n Blending Ratio Register (PnALPHAR) (n = 1 to 6)
- 19.3.34 Plane n Display Size X Register (PnDSXR) (n = 1 to 6)
- 19.3.35 Plane n Display Size Y Register (PnDSYR) (n = 1 to 6)
- 19.3.36 Plane n Display Position X Register (PnDPXR) (n = 1 to 6)
- 19.3.37 Plane n Display Position Y Register (PnDPYR) (n = 1 to 6)
- 19.3.38 Plane n Display Area Start Address 0 Register (PnDSA0R) (n = 1 to 6)
- 19.3.39 Plane n Display Area Start Address 1 Register (PnDSA1R) (n = 1 to 6)
- 19.3.40 Plane n Start Position X Register (PnSPXR) (n = 1 to 6)
- 19.3.41 Plane n Start Position Y Register (PnSPYR) (n = 1 to 6)
- 19.3.42 Plane n Wrap Around Start Position Register (PnWASPR) (n = 1 to 6)
- 19.3.43 Plane n Wrap Around Memory Width Register (PnWAMWR) (n = 1 to 6)
- 19.3.44 Plane n Blinking Time Register (PnBTR) (n = 1 to 6)
- 19.3.45 Plane n Transparent Color 1 Register (PnTC1R) (n = 1 to 6)
- 19.3.46 Plane n Transparent Color 2 Register (PnTC2R) (n = 1 to 6)
- 19.3.47 Plane n Memory Length Register (PnMLR) (n = 1 to 6)
- 19.3.48 Color Palette 1 Register 000 to 255 (CP1_000R to CP1_255R)
- 19.3.49 Color Palette 2 Register 000 to 255 (CP2_000R to CP2_255R)
- 19.3.50 Color Palette 3 Register 000 to 255 (CP3_000R to CP3_255R)
- 19.3.51 Color Palette 4 Register 000 to 255 (CP4_000R to CP4_255R)
- 19.3.52 External Synchronization Control Register (ESCR)
- 19.3.53 Output Signal Timing Adjustment Register (OTAR)
- 19.4 Operation
- 19.4.1 Configuration of Output Screen
- 19.4.2 Display On/Off
- 19.4.3 Plane Parameter
- 19.4.4 Memory Allocation
- 19.4.5 Input Display Data Format
- 19.4.6 Output Data Format
- 19.4.7 Endian Conversion
- 19.4.8 Color Palettes
- 19.4.9 Superpositioning of Planes
- 19.4.10 Display Contention
- 19.4.11 Blinking
- 19.4.12 Scroll Display
- 19.4.13 Wraparound Display
- 19.4.14 Upper-Left Overflow Display
- 19.4.15 Double Buffer Control
- 19.4.16 Sync Mode
- 19.5 Display Control
- 19.6 Power-Down Sequence
- Section 20 Graphics Data Translation Accelerator (GDTA)
- 20.1 Features
- 20.2 GDTA Address Space
- 20.3 Register Descriptions
- 20.3.1 GA Mask Register (GACMR)
- 20.3.2 GA Enable Register (GACER)
- 20.3.3 GA Interrupt Source Indicating Register (GACISR)
- 20.3.4 GA Interrupt Source Indication Clear Register (GACICR)
- 20.3.5 GA Interrupt Enable Register (GACIER)
- 20.3.6 GA CL Input Data Alignment Register (DRCL_CTL)
- 20.3.7 GA CL Output Data Alignment Register (DWCL_CTL)
- 20.3.8 GA MC Input Data Alignment Register (DRMC_CTL)
- 20.3.9 GA MC Output Data Alignment Register (DWMC_CTL)
- 20.3.10 GA Buffer RAM 0 Data Alignment Register (DCP_CTL)
- 20.3.11 GA Buffer RAM 1 Data Alignment Register (DID_CTL)
- 20.3.12 CL Command FIFO (CLCF)
- 20.3.13 CL Control Register (CLCR)
- 20.3.14 CL Status Register (CLSR)
- 20.3.15 CL Frame Width Setting Register (CLWR)
- 20.3.16 CL Frame Height Setting Register (CLHR)
- 20.3.17 CL Input Y Padding Size Setting Register (CLIYPR)
- 20.3.18 CL Input UV Padding Size Setting Register (CLIUVPR)
- 20.3.19 CL Output Padding Size Setting Register (CLOPR)
- 20.3.20 CL Palette Pointer Register (CLPLPR)
- 20.3.21 MC Command FIFO (MCCF)
- 20.3.22 MC Status Register (MCSR)
- 20.3.23 MC Frame Width Setting Register (MCWR)
- 20.3.24 MC Frame Height Setting Register (MCHR)
- 20.3.25 MC Y Padding Size Setting Register (MCYPR)
- 20.3.26 MC UV Padding Size Setting Register (MCUVPR)
- 20.3.27 MC Output Frame Y Pointer Register (MCOYPR)
- 20.3.28 MC Output Frame U Pointer Register (MCOUPR)
- 20.3.29 MC Output Frame V Pointer Register (MCOVPR)
- 20.3.30 MC Past Frame Y Pointer Register (MCPYPR)
- 20.3.31 MC Past Frame U Pointer Register (MCPUPR)
- 20.3.32 MC Past Frame V Pointer Register (MCPVPR)
- 20.3.33 MC Future Frame Y Pointer Register (MCFYPR)
- 20.3.34 MC Future Frame U Pointer Register (MCFUPR)
- 20.3.35 MC Future Frame V Pointer Register (MCFVPR)
- 20.4 GDTA Operation
- 20.5 Interrupt Processing
- 20.6 Data Alignment
- 20.7 Usage Notes
- Section 21 Serial Communication Interface with FIFO (SCIF)
- 21.1 Features
- 21.2 Input/Output Pins
- 21.3 Register Descriptions
- 21.3.1 Receive Shift Register (SCRSR)
- 21.3.2 Receive FIFO Data Register (SCFRDR)
- 21.3.3 Transmit Shift Register (SCTSR)
- 21.3.4 Transmit FIFO Data Register (SCFTDR)
- 21.3.5 Serial Mode Register (SCSMR)
- 21.3.6 Serial Control Register (SCSCR)
- 21.3.7 Serial Status Register n (SCFSR)
- 21.3.8 Bit Rate Register n (SCBRR)
- 21.3.9 FIFO Control Register n (SCFCR)
- 21.3.10 Transmit FIFO Data Count Register n (SCTFDR)
- 21.3.11 Receive FIFO Data Count Register n (SCRFDR)
- 21.3.12 Serial Port Register n (SCSPTR)
- 21.3.13 Line Status Register n (SCLSR)
- 21.3.14 Serial Error Register n (SCRER)
- 21.4 Operation
- 21.5 SCIF Interrupt Sources and the DMAC
- 21.6 Usage Notes
- Section 22 Serial I/O with FIFO (SIOF)
- 22.1 Features
- 22.2 Input/Output Pins
- 22.3 Register Descriptions
- 22.3.1 Mode Register (SIMDR)
- 22.3.2 Control Register (SICTR)
- 22.3.3 Transmit Data Register (SITDR)
- 22.3.4 Receive Data Register (SIRDR)
- 22.3.5 Transmit Control Data Register (SITCR)
- 22.3.6 Receive Control Data Register (SIRCR)
- 22.3.7 Status Register (SISTR)
- 22.3.8 Interrupt Enable Register (SIIER)
- 22.3.9 FIFO Control Register (SIFCTR)
- 22.3.10 Clock Select Register (SISCR)
- 22.3.11 Transmit Data Assign Register (SITDAR)
- 22.3.12 Receive Data Assign Register (SIRDAR)
- 22.3.13 Control Data Assign Register (SICDAR)
- 22.4 Operation
- Section 23 Serial Peripheral Interface (HSPI)
- 23.1 Features
- 23.2 Input/Output Pins
- 23.3 Register Descriptions
- 23.4 Operation
- 23.4.1 Operation Overview with FIFO Mode Disabled
- 23.4.2 Operation with FIFO Mode Enabled
- 23.4.3 Timing Diagrams
- 23.4.4 HSPI Software Reset
- 23.4.5 Clock Polarity and Transmit Control
- 23.4.6 Transmit and Receive Routines
- 23.4.7 Flags and Interrupt Timing
- 23.4.8 Low-Power Consumption and Clock Synchronization
- Section 24 Multimedia Card Interface (MMCIF)
- 24.1 Features
- 24.2 Input/Output Pins
- 24.3 Register Descriptions
- 24.3.1 Command Registers 0 to 5 (CMDR0 to CMDR5)
- 24.3.2 Command Start Register (CMDSTRT)
- 24.3.3 Operation Control Register (OPCR)
- 24.3.4 Card Status Register (CSTR)
- 24.3.5 Interrupt Control Registers 0 to 2 (INTCR0 to INTCR2)
- 24.3.6 Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2)
- 24.3.7 Transfer Clock Control Register (CLKON)
- 24.3.8 Command Timeout Control Register (CTOCR)
- 24.3.9 Transfer Byte Number Count Register (TBCR)
- 24.3.10 Mode Register (MODER)
- 24.3.11 Command Type Register (CMDTYR)
- 24.3.12 Response Type Register (RSPTYR)
- 24.3.13 Transfer Block Number Counter (TBNCR)
- 24.3.14 Response Registers 0 to 16, D (RSPR0 to RSPR16, RSPRD)
- 24.3.15 Data Timeout Register (DTOUTR)
- 24.3.16 Data Register (DR)
- 24.3.17 FIFO Pointer Clear Register (FIFOCLR)
- 24.3.18 DMA Control Register (DMACR)
- 24.4 Operation
- 24.5 MMCIF Interrupt Sources
- 24.6 Operations when Using DMA
- 24.7 Register Accesses with Little Endian Specification
- Section 25 Audio Codec Interface (HAC)
- 25.1 Features
- 25.2 Input/Output Pins
- 25.3 Register Descriptions
- 25.3.1 Control and Status Register (HACCR)
- 25.3.2 Command/Status Address Register (HACCSAR)
- 25.3.3 Command/Status Data Register (HACCSDR)
- 25.3.4 PCM Left Channel Register (HACPCML)
- 25.3.5 PCM Right Channel Register (HACPCMR)
- 25.3.6 TX Interrupt Enable Register (HACTIER)
- 25.3.7 TX Status Register (HACTSR)
- 25.3.8 RX Interrupt Enable Register (HACRIER)
- 25.3.9 RX Status Register (HACRSR)
- 25.3.10 HAC Control Register (HACACR)
- 25.4 AC 97 Frame Slot Structure
- 25.5 Operation
- Section 26 Serial Sound Interface (SSI) Module
- Section 27 NAND Flash Memory Controller (FLCTL)
- 27.1 Features
- 27.2 Input/Output Pins
- 27.3 Register Descriptions
- 27.3.1 Common Control Register (FLCMNCR)
- 27.3.2 Command Control Register (FLCMDCR)
- 27.3.3 Command Code Register (FLCMCDR)
- 27.3.4 Address Register (FLADR)
- 27.3.5 Address Register 2 (FLADR2)
- 27.3.6 Data Counter Register (FLDTCNTR)
- 27.3.7 Data Register (FLDATAR)
- 27.3.8 Interrupt DMA Control Register (FLINTDMACR)
- 27.3.9 Ready Busy Timeout Setting Register (FLBSYTMR)
- 27.3.10 Ready Busy Timeout Counter (FLBSYCNT)
- 27.3.11 Data FIFO Register (FLDTFIFO)
- 27.3.12 Control Code FIFO Register (FLECFIFO)
- 27.3.13 Transfer Control Register (FLTRCR)
- 27.4 Operation
- 27.5 Example of Register Setting
- 27.6 Interrupt Processing
- 27.7 DMA Transfer Settings
- Section 28 General Purpose I/O Ports (GPIO)
- 28.1 Features
- 28.2 Register Descriptions
- 28.2.1 Port A Control Register (PACR)
- 28.2.2 Port B Control Register (PBCR)
- 28.2.3 Port C Control Register (PCCR)
- 28.2.4 Port D Control Register (PDCR)
- 28.2.5 Port E Control Register (PECR)
- 28.2.6 Port F Control Register (PFCR)
- 28.2.7 Port G Control Register (PGCR)
- 28.2.8 Port H Control Register (PHCR)
- 28.2.9 Port J Control Register (PJCR)
- 28.2.10 Port K Control Register (PKCR)
- 28.2.11 Port L Control Register (PLCR)
- 28.2.12 Port M Control Register (PMCR)
- 28.2.13 Port N Control Register (PNCR)
- 28.2.14 Port P Control Register (PPCR)
- 28.2.15 Port Q Control Register (PQCR)
- 28.2.16 Port R Control Register (PRCR)
- 28.2.17 Port A Data Register (PADR)
- 28.2.18 Port B Data Register (PBDR)
- 28.2.19 Port C Data Register (PCDR)
- 28.2.20 Port D Data Register (PDDR)
- 28.2.21 Port E Data Register (PEDR)
- 28.2.22 Port F Data Register (PFDR)
- 28.2.23 Port G Data Register (PGDR)
- 28.2.24 Port H Data Register (PHDR)
- 28.2.25 Port J Data Register (PJDR)
- 28.2.26 Port K Data Register (PKDR)
- 28.2.27 Port L Data Register (PLDR)
- 28.2.28 Port M Data Register (PMDR)
- 28.2.29 Port N Data Register (PNDR)
- 28.2.30 Port P Data Register (PPDR)
- 28.2.31 Port Q Data Register (PQDR)
- 28.2.32 Port R Data Register (PRDR)
- 28.2.33 Port E Pull-Up Control Register (PEPUPR)
- 28.2.34 Port H Pull-Up Control Register (PHPUPR)
- 28.2.35 Port J Pull-Up Control Register (PJPUPR)
- 28.2.36 Port K Pull-Up Control Register (PKPUPR)
- 28.2.37 Port L Pull-Up Control Register (PLPUPR)
- 28.2.38 Port M Pull-Up Control Register (PMPUPR)
- 28.2.39 Port N Pull-Up Control Register (PNPUPR)
- 28.2.40 Input-Pin Pull-Up Control Register 1 (PPUPR1)
- 28.2.41 Input-Pin Pull-Up Control Register 2 (PPUPR2)
- 28.2.42 Peripheral Module Select Register 1 (P1MSELR)
- 28.2.43 Peripheral Module Select Register 2 (P2MSELR)
- 28.3 Usage Example
- Section 29 User Break Controller (UBC)
- 29.1 Features
- 29.2 Register Descriptions
- 29.2.1 Match Condition Setting Registers 0 and 1 (CBR0 and CBR1)
- 29.2.2 Match Operation Setting Registers 0 and 1 (CRR0 and CRR1)
- 29.2.3 Match Address Setting Registers 0 and 1 (CAR0 and CAR1)
- 29.2.4 Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1)
- 29.2.5 Match Data Setting Register 1 (CDR1)
- 29.2.6 Match Data Mask Setting Register 1 (CDMR1)
- 29.2.7 Execution Count Break Register 1 (CETR1)
- 29.2.8 Channel Match Flag Register (CCMFR)
- 29.2.9 Break Control Register (CBCR)
- 29.3 Operation Description
- 29.4 User Break Debugging Support Function
- 29.5 User Break Examples
- 29.6 Usage Notes
- Section 30 User Debugging Interface (H-UDI)
- Section 31 Register List
- Section 32 Electrical Characteristics
- 32.1 Absolute Maximum Ratings
- 32.2 DC Characteristics
- 32.3 AC Characteristics
- 32.3.1 Clock and Control Signal Timing
- 32.3.2 Control Signal Timing
- 32.3.3 Bus Timing
- 32.3.4 DBSC2 Signal Timing
- 32.3.5 INTC Module Signal Timing
- 32.3.6 PCIC Module Signal Timing
- 32.3.7 DMAC Module Signal Timing
- 32.3.8 TMU Module Signal Timing
- 32.3.9 SCIF Module Signal Timing
- 32.3.10 H-UDI Module Signal Timing
- 32.3.11 GPIO Signal Timing
- 32.3.12 HSPI Module Signal Timing
- 32.3.13 SIOF Module Signal Timing
- 32.3.14 MMCIF Module Signal Timing
- 32.3.15 HAC Interface Module Signal Timing
- 32.3.16 SSI Interface Module Signal Timing
- 32.3.17 FLCTL Module Signal Timing
- 32.3.18 Display Unit Signal Timing
- 32.4 AC Characteristic Test Conditions
- Appendix
- Colophon