Renesas SH7781 User Manual

Page 1065

21. Serial Communication Interface with FIFO (SCIF)

Rev.1.00 Jan. 10, 2008 Page 1035 of 1658

REJ09B0261-0100

Figure 21.1 shows a block diagram of the SCIF. Figures 21.2 to 21.6 show block diagrams of the
I/O ports in the SCIF. There are six channels in this LSI. In figures 21.2 to 21.6, the channel
number is omitted.

SCFRDRn (128 stages)

SCRSRn

SCIFn_RXD

SCIFn_TXD

SCIFn_SCK

SCIF0_CTS

SCIF0_RTS

SCFTDRn (128 stages)

SCTSRn

SCTFDRn
SCRFDRn

SCFCRn

SCFSRn

SCSCRn

SCSPTRn
SCRERn

SCLSRn

SCSMRn

SCBRRn

Pck

Pck/4

Pck/16

Pck/64

SCIF

Parity generation

Parity check

Module data bus

Transmission/
reception control

Clock

Baud rate generator

Peripheral bus

External clock

Bus interface

(64 stages)

Legend:
SCRSRn:

Receive shift register

SCFRDRn:

Receive FIFO data register

SCTSRn:

Transmit shift register

SCFTDRn:

Transmit FIFO data register

SCSMRn:

Serial mode register

SCSCRn:

Serial control register

SCFSRn:

Serial status register

SCBRRn:

Bit rate register

SCSPTRn:

Serial port register

SCFCRn:

FIFO control register

SCTFDRn: Transmit FIFO data count register
SCRFDRn: Receive FIFO data count register
SCLSRn:

Line status register

SCRERn:

Serial error register

Note: n = 0 to 5
Channels 1 to 5 do not have

SCIF1_CTS to SCIF5_CTS and SCIF1_RTS to SCIF5_RTS.

TXIn
RXIn
ERIn
BRIn

Figure 21.1 Block Diagram of SCIF

Figures 21.2 to 21.6 show block diagrams of the I/O ports in SCIF.