Renesas SH7781 - Manual (Page 735)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 705 of 1658
REJ09B0261-0100
CHCR DMARS
RS[3:0] MID RID
DMA Transfer
Request Source DMA Transfer Request Signal Source
Destination
Bus
Mode
1000 001101 01 SCIF5 transmitter TXI (transmit FIFO data empty) Any SCFTDR5 Cycle
steal
10 SCIF5 receiver RXI (receive FIFO data full) SCFRDR5 Any Cycle
steal
010000 01 HAC0 transmitter Transmit data empty request Any HACPCML0,
HACPCMR0 Cycle
steal
10 HAC0 receiver Unread receive data is present HACPCML0,
HACPCMR0
Any Cycle
steal
010001 01 HAC1 transmitter Transmit data empty request Any HACPCML1,
HACPCMR1 Cycle
steal
10 HAC1 receiver Unread receive data is present HACPCML1,
HACPCMR1
Any Cycle
steal
010100 01 SIOF transmitter Transmit FIFO data empty
request
Any SITDR Cycle
steal
10 SIOF receiver Receive FIFO data full request SIRDR Any Cycle
steal
100000 11 FLCTL data part
transmitter Transmit FIFO data empty
request Any FLDTFIFO Cycle
steal
FLCTL data part
receiver Receive FIFO data full request FLDTFIFO Any Cycle
steal
100001 11 FLCTL
management
code part
transmitter Transmit FIFO data empty
request Any FLECFIFO Cycle
steal
FLCTL
management
code part receiver Receive FIFO data full request FLECFIFO Any Cycle
steal
100100 11 MMCIF data part
transmitter
FIFO write request Any DR Cycle
steal
MMCIF data part
receiver
FIFO read request DR Any Cycle
steal
101000 01 HSPI transmitter Transmit data Any SPTBR Cycle
steal
10 HSPI receiver Receive data SPRBR Any Cycle
steal