Renesas SH7781 - Manual (Page 1156)

22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1126 of 1658
REJ09B0261-0100
22.3.13 Control Data Assign Register (SICDAR)
SICDAR is a 16-bit readable/writable register that specifies the position of the control data in a
frame. SICDAR can be specified only when the FL bits in SIMDR are set to 1xxx (x: don't care.).
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CD1 A[3:0] — — — CD1E CD0 A[3:0] — CD0E —
R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R R R/W R
BIt:
Initial value:
R/W:
—
Bit Bit Name
Initial
Value R/W Description
15 CD0E 0 R/W Control Channel 0 Data Enable
0: Disables transmission and reception of control
channel 0 data
1: Enables transmission and reception of control
channel 0 data
14 to 12
⎯ All
0 R Reserved
These bits are always read as 0. The write value should
always be 0.
11 to 8 CD0A[3:0] 0000 R/W Control Channel 0 Data Assigns 3 to 0
These bits specify the position of control channel 0 data
in a receive or transmit frame as B'0000 (0) to B'1110
(14).
1111: Setting prohibited
• Transmit data for the control channel 0 data is
specified in the SITD0 bit in SITCR.
• Receive data for the control channel 0 data is stored
in the SIRD0 bit in SIRCR.
7 CD1E 0 R/W Control Channel 1 Data Enable
0: Disables transmission and reception of control
channel 1 data
1: Enables transmission and reception of control
channel 1 data
6 to 4
⎯ All
0 R Reserved
These bits are always read as 0. The write value should
always be 0.