beautypg.com

9 fifo control register (sifctr) – Renesas SH7781 User Manual

Page 1150

background image

22. Serial I/O with FIFO (SIOF)

Rev.1.00 Jan. 10, 2008 Page 1120 of 1658
REJ09B0261-0100

22.3.9

FIFO Control Register (SIFCTR)

SIFCTR is a 16-bit readable/writable register that indicates the area available for the
transmit/receive FIFO transfer.

0

1

2

3

4

5

6

7

8

9

10

11

12

13

15

14

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

RFUA[4:0]

RFWM[2:0]

TFUA[4:0]

TFWM[2:0]

R

R

R

R

R

R/W

R/W

R/W

R

R

R

R

R

R/W

R/W

R/W

BIt:

Initial value:

R/W:

Bit Bit

Name

Initial
Value R/W Description

15 to 13 TFWM[2:0] 000

R/W

Transmit FIFO Watermark

000: Issue a transfer request when 16 stages of the

transmit FIFO are empty.

001: Setting prohibited

010: Setting prohibited

011: Setting prohibited

100: Issue a transfer request when 12 or more stages

of the transmit FIFO are empty.

101: Issue a transfer request when 8 or more stages of

the transmit FIFO are empty.

110: Issue a transfer request when 4 or more stages of

the transmit FIFO are empty.

111: Issue a transfer request when 1 or more stages of

transmit FIFO are empty. Setting prohibited when
using the DMA transfer.

• A transfer request to the transmit FIFO is issued by

the TDREQE bit in SISTR.

• The transmit FIFO is always used as 16 stages of

the FIFO regardless of these bit settings.

12 to 8

TFUA[4:0]

10000

R

Transmit FIFO Usable Area

These bits indicate the number of words that can be
transferred by the CPU or DMAC as B'00000 (full) to
B'10000 (empty).