Renesas SH7781 - Manual (Page 403)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 373 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value
R/W Description
23
⎯ 0
R Reserved
This bit is always read as 0. The write value should
always be 0.
22 to 20 IWRWS 111 R/W Idle Cycles between Read-Write in Same Space
These bits specify the number of idle cycles to be
inserted after the access to the memory connected to
the space. The target cycles are read-write cycles in
which consecutive accesses are performed to the same
space. For details, see section 11.5.8, Wait Cycles
between Access Cycles.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 3 idle cycles inserted
100: 4 idle cycles inserted
101: 5 idle cycles inserted
110: 6 idle cycles inserted
111: 7 idle cycles inserted
19
⎯ 0
R Reserved
This bit is always read as 0. The write value should
always be 0.
18 to 16 IWRRD 111 R/W Idle Cycles between Read-Read in Different Spaces
These bits specify the number of idle cycles to be
inserted after the memory connected to the space is
accessed. The target cycles are read-read cycles in
which consecutive accesses are performed to different
spaces. For details, see section 11.5.8, Wait Cycles
between Access Cycles.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 3 idle cycles inserted
100: 4 idle cycles inserted
101: 5 idle cycles inserted
110: 6 idle cycles inserted
111: 7 idle cycles inserted