Renesas SH7781 - Manual (Page 321)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 291 of 1658
REJ09B0261-0100
(8) Interrupt Mask Clear Register 0 (INTMSKCLR0)
INTMSKCLR0 is a 32-bit write-only register that clears the mask settings for each of the interrupt
requests IRQn (n = 0 to 7). Undefined values are read from this register.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IC07 IC06 IC05 IC04 IC03 IC02 IC00 IC01
R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R R R R R R R R R R R R R R R R
Bit:
Initial value:
R/W:
Bit Name
Initial
Value R/W Description
31 IC00 0 R/W Clears masking of IRQ0
interrupt.
30 IC01 0 R/W Clears masking of IRQ1
interrupt.
29 IC02 0 R/W Clears masking of IRQ2
interrupt.
28 IC03 0 R/W Clears masking of IRQ3
interrupt.
27 IC04 0 R/W Clears masking of IRQ4
interrupt.
26 IC05 0 R/W Clears masking of IRQ5
interrupt.
25 IC06 0 R/W Clears masking of IRQ6
interrupt.
24 IC07 0 R/W Clears masking of IRQ7
interrupt.
[When read]
Undefined values are
read.
[When written]
0: No effect
1: Clears the
corresponding interrupt
mask (enables the
interrupt)
23 to 0 — All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.