Renesas SH7781 - Manual (Page 458)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 428 of 1658
REJ09B0261-0100
CLKOUT
CSn
BS
RD
R/ W
D31 to D0
RDY
SH7785 MPX device
CLK
CS
BS
FRAME
WE
I/O31 to I/O0
RDY
Figure 11.22 Example of 32-Bit Data Width MPX Connection
CLKOUT
CSn
BS
RD
RD/ WR
D63 to D0
RDY
SH7785 MPX device
CLK
CS
BS
FRAME
WE
I/O63 to I/O0
RDY
Figure 11.23 Example of 64-Bit Data Width MPX Connection
The MPX interface timing is shown below.
When the MPX interface is used for area 0, the bus size should be set to 64 or 32 bits by MODE5
and MODE6. When the MPX interface is used for areas 1 to 6, the bus size should be set to 32 or
64 bits by CSnBCR.
Waits can be inserted by CSnWCR and the
RDY pin.
In reading, one wait cycle is automatically inserted after address output even if CSnWCR is
cleared to 0.